SN65LVDS104PWR データシート Ti

SN65LVDS104PWR - TI の商品詳細ページです。

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SN65LVDS104PWR の詳細情報

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型番SN65LVDS104PWR
メーカーTI
データシートProduct_list_pdf
Family LVDS
Input Conditioning DIFFERENTIAL
JESD-30 Code R-PDSO-G16
JESD-609 Code e4
Length 5 mm
Load Capacitance (CL) 10 pF
Logic IC Type LOW SKEW CLOCK DRIVER
Moisture Sensitivity Level 1
Number of Functions 1
Number of Inverted Outputs 0
Number of Terminals 16
Number of True Outputs 8
Operating Temperature-Max 85 Cel
Operating Temperature-Min -40 Cel
Output Characteristics 3-STATE
Package Body Material PLASTIC/EPOXY
Package Code TSSOP
Package Equivalence Code TSSOP16,.25
Package Shape RECTANGULAR
Package Style SMALL OUTLINE, THIN PROFILE, SHRINK PITCH Meter
Packing Method TR
Peak Reflow Temperature (Cel) 260
Power Supplies 3.3 V
Prop. Delay@Nom-Sup 4.2 ns
Propagation Delay (tpd) 4.2 ns
Qualification Status Not Qualified
Seated Height-Max 1.2 mm
Sub Category Clock Drivers
Supply Voltage-Max (Vsup) 3.6 V
Supply Voltage-Min (Vsup) 3 V
Supply Voltage-Nom (Vsup) 3.3 V
Surface Mount YES
Temperature Grade INDUSTRIAL
Terminal Finish Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal Form GULL WING
Terminal Pitch 0.65 mm
Terminal Position DUAL
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
Width 4.4 mm
会社名称Texas Instruments Incorporated.
設立1930
資本金USD 816 million
所在地12500 TI Boulevard Dallas, Texas 75243 USA
URLhttp://www.ti.com/

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