M5LV-512/256-7SAC データシート Lattice

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M5LV-512/256-7SAC の詳細情報

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型番M5LV-512/256-7SAC
メーカーLATTICE
データシートProduct_list_pdf
Additional Feature YES
Clock Frequency-Max 100 MHz
In-System Programmable YES
JESD-30 Code S-PBGA-B352
JESD-609 Code e0
JTAG BST YES
Length 35 mm
Moisture Sensitivity Level 3
Number of Dedicated Inputs 0
Number of I/O Lines 256
Number of Macro Cells 512
Number of Terminals 352
Operating Temperature-Max 70 Cel
Operating Temperature-Min 0 Cel
Organization 0 DEDICATED INPUTS, 256 I/O
Output Function MACROCELL
Package Body Material PLASTIC/EPOXY
Package Code LBGA
Package Equivalence Code BGA352,26X26,50
Package Shape SQUARE
Package Style GRID ARRAY, LOW PROFILE Meter
Peak Reflow Temperature (Cel) 225
Power Supplies 3.3 V
Programmable Logic Type EE PLD
Propagation Delay 7.5 ns
Qualification Status Not Qualified
Seated Height-Max 1.7 mm
Sub Category Programmable Logic Devices
Supply Voltage-Max 3.6 V
Supply Voltage-Min 3 V
Supply Voltage-Nom 3.3 V
Surface Mount YES
Technology CMOS
Temperature Grade COMMERCIAL
Terminal Finish Tin/Lead (Sn63Pb37)
Terminal Form BALL
Terminal Pitch 1.27 mm
Terminal Position BOTTOM
Time@Peak Reflow Temperature-Max (s) 30
Width 35 mm
会社名称Lattice Semiconductor Corporation
設立1983
所在地7th Floor, 111 SW 5th Avenue, Portland OR 97204
URLhttp://www.latticesemi.com/

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