LFE2-12E-5F256I データシート Lattice

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LFE2-12E-5F256I の詳細情報

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型番LFE2-12E-5F256I
メーカーLATTICE
データシートProduct_list_pdf
Clock Frequency-Max 311 MHz
Combinatorial Delay of a CLB-Max 0.358 ns
JESD-30 Code S-PBGA-B256
JESD-609 Code e0
Length 17 mm
Moisture Sensitivity Level 3
Number of Inputs 193
Number of Logic Cells 12000
Number of Outputs 193
Number of Terminals 256
Operating Temperature-Max 85 Cel
Operating Temperature-Min -40 Cel
Package Body Material PLASTIC/EPOXY
Package Code BGA
Package Equivalence Code BGA256,16X16,40
Package Shape SQUARE
Package Style GRID ARRAY Meter
Peak Reflow Temperature (Cel) 225
Power Supplies 1.2 V
Programmable Logic Type FIELD PROGRAMMABLE GATE ARRAY
Qualification Status Not Qualified
Seated Height-Max 2.1 mm
Sub Category Field Programmable Gate Arrays
Supply Voltage-Max 1.26 V
Supply Voltage-Min 1.14 V
Supply Voltage-Nom 1.2 V
Surface Mount YES
Temperature Grade INDUSTRIAL
Terminal Finish TIN LEAD
Terminal Form BALL
Terminal Pitch 1 mm
Terminal Position BOTTOM
Time@Peak Reflow Temperature-Max (s) 30
Width 17 mm
会社名称Lattice Semiconductor Corporation
設立1983
所在地7th Floor, 111 SW 5th Avenue, Portland OR 97204
URLhttp://www.latticesemi.com/

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