LC51024MV-52FN672C データシート Lattice

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LC51024MV-52FN672C の詳細情報

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型番LC51024MV-52FN672C
メーカーLATTICE
データシートProduct_list_pdf
Additional Feature YES
In-System Programmable YES
JESD-30 Code S-PBGA-B672
JESD-609 Code e1
JTAG BST YES
Length 27 mm
Moisture Sensitivity Level 3
Number of Dedicated Inputs 0
Number of I/O Lines 381
Number of Macro Cells 1024
Number of Terminals 672
Organization 0 DEDICATED INPUTS, 381 I/O
Output Function MACROCELL
Package Body Material PLASTIC/EPOXY
Package Code BGA
Package Equivalence Code BGA672,26X26,40
Package Shape SQUARE
Package Style GRID ARRAY Meter
Peak Reflow Temperature (Cel) 250
Power Supplies 3.3 V
Programmable Logic Type EE PLD
Propagation Delay 6.5 ns
Qualification Status Not Qualified
Seated Height-Max 2.6 mm
Sub Category Programmable Logic Devices
Supply Voltage-Max 3.6 V
Supply Voltage-Min 3 V
Supply Voltage-Nom 3.3 V
Surface Mount YES
Technology CMOS
Terminal Finish Tin/Silver/Copper (Sn/Ag/Cu)
Terminal Form BALL
Terminal Pitch 1 mm
Terminal Position BOTTOM
Time@Peak Reflow Temperature-Max (s) 40
Width 27 mm
会社名称Lattice Semiconductor Corporation
設立1983
所在地7th Floor, 111 SW 5th Avenue, Portland OR 97204
URLhttp://www.latticesemi.com/

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