LC4512B-35F256C データシート Lattice

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LC4512B-35F256C の詳細情報

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型番LC4512B-35F256C
メーカーLATTICE
データシートProduct_list_pdf
Architecture PAD-TYPE
Clock Frequency-Max 212 MHz
In-System Programmable YES
JESD-30 Code S-PBGA-B256
JESD-609 Code e0
JTAG BST YES
Length 17 mm
Moisture Sensitivity Level 3
Number of Dedicated Inputs 4
Number of I/O Lines 208
Number of Inputs 212
Number of Macro Cells 512
Number of Outputs 208
Number of Product Terms 83
Number of Terminals 256
Operating Temperature-Max 90 Cel
Operating Temperature-Min 0 Cel
Organization 4 DEDICATED INPUTS, 208 I/O
Output Function MACROCELL
Package Body Material PLASTIC/EPOXY
Package Code BGA
Package Equivalence Code BGA256,16X16,40
Package Shape SQUARE
Package Style GRID ARRAY Meter
Peak Reflow Temperature (Cel) 225
Power Supplies 2.5 V
Programmable Logic Type EE PLD
Propagation Delay 3.5 ns
Qualification Status Not Qualified
Seated Height-Max 2.1 mm
Sub Category Programmable Logic Devices
Supply Voltage-Max 2.7 V
Supply Voltage-Min 2.3 V
Supply Voltage-Nom 2.5 V
Surface Mount YES
Terminal Finish Tin/Lead (Sn63Pb37)
Terminal Form BALL
Terminal Pitch 1 mm
Terminal Position BOTTOM
Time@Peak Reflow Temperature-Max (s) 30
Width 17 mm
会社名称Lattice Semiconductor Corporation
設立1983
所在地7th Floor, 111 SW 5th Avenue, Portland OR 97204
URLhttp://www.latticesemi.com/

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