GAL26CV12B-15LP Lattice

GAL26CV12B-15LP - LATTICE の商品詳細ページです。

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GAL26CV12B-15LP の詳細情報

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型番GAL26CV12B-15LP
メーカーLATTICE
Additional Feature REGISTER PRELOAD; POWER-UP RESET
Architecture PAL-TYPE
Clock Frequency-Max 55.5 MHz
JESD-30 Code R-PDIP-T28
JESD-609 Code e0
Length 34.671 mm
Number of Dedicated Inputs 13
Number of I/O Lines 12
Number of Inputs 26
Number of Outputs 12
Number of Product Terms 122
Number of Terminals 28
Operating Temperature-Max 75 Cel
Operating Temperature-Min -40 Cel
Organization 13 DEDICATED INPUTS, 12 I/O
Output Function MACROCELL
Package Body Material PLASTIC/EPOXY
Package Code DIP
Package Equivalence Code DIP28,.3
Package Shape RECTANGULAR
Package Style IN-LINE Meter
Power Supplies 5 V
Programmable Logic Type EE PLD
Propagation Delay 15 ns
Qualification Status Not Qualified
Seated Height-Max 4.57 mm
Sub Category Programmable Logic Devices
Supply Voltage-Max 5.25 V
Supply Voltage-Min 4.5 V
Supply Voltage-Nom 5 V
Surface Mount NO
Technology CMOS
Temperature Grade COMMERCIAL EXTENDED
Terminal Finish Tin/Lead (Sn85Pb15)
Terminal Form THROUGH-HOLE
Terminal Pitch 2.54 mm
Terminal Position DUAL
Width 7.62 mm
会社名称Lattice Semiconductor Corporation
設立1983
所在地7th Floor, 111 SW 5th Avenue, Portland OR 97204
URLhttp://www.latticesemi.com/

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