GAL20V8A-12LP データシート Lattice

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GAL20V8A-12LP の詳細情報

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型番GAL20V8A-12LP
メーカーLATTICE
データシートProduct_list_pdf
Architecture PAL-TYPE
Clock Frequency-Max 62.5 MHz
JESD-30 Code R-PDIP-T24
JESD-609 Code e0
Number of Inputs 20
Number of Outputs 8
Number of Product Terms 64
Number of Terminals 24
Operating Temperature-Max 70 Cel
Operating Temperature-Min 0 Cel
Output Function MACROCELL
Package Body Material PLASTIC/EPOXY
Package Code DIP
Package Equivalence Code DIP24,.3
Package Shape RECTANGULAR
Package Style IN-LINE Meter
Power Supplies 5 V
Programmable Logic Type EE PLD
Propagation Delay 12 ns
Qualification Status Not Qualified
Sub Category Programmable Logic Devices
Supply Voltage-Nom 5 V
Surface Mount NO
Technology CMOS
Temperature Grade COMMERCIAL
Terminal Finish Tin/Lead (Sn85Pb15)
Terminal Form THROUGH-HOLE
Terminal Pitch 2.54 mm
Terminal Position DUAL
会社名称Lattice Semiconductor Corporation
設立1983
所在地7th Floor, 111 SW 5th Avenue, Portland OR 97204
URLhttp://www.latticesemi.com/

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