GAL18V10B-15LPN データシート Lattice

GAL18V10B-15LPN - LATTICE の商品詳細ページです。

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GAL18V10B-15LPN の詳細情報

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型番GAL18V10B-15LPN
メーカーLATTICE
データシートProduct_list_pdf
Additional Feature REGISTER PRELOAD; POWER-ON RESET
Architecture PAL-TYPE
Clock Frequency-Max 55.5 MHz
In-System Programmable NO
JESD-30 Code R-PDIP-T20
JTAG BST NO
Length 26.162 mm
Number of Dedicated Inputs 7
Number of I/O Lines 10
Number of Inputs 18
Number of Macro Cells 10
Number of Outputs 10
Number of Product Terms 96
Number of Terminals 20
Operating Temperature-Max 75 Cel
Operating Temperature-Min 0 Cel
Organization 7 DEDICATED INPUTS, 10 I/O
Output Function MACROCELL
Package Body Material PLASTIC/EPOXY
Package Code DIP
Package Equivalence Code DIP20,.3
Package Shape RECTANGULAR
Package Style IN-LINE Meter
Programmable Logic Type EE PLD
Propagation Delay 15 ns
Seated Height-Max 5.334 mm
Supply Voltage-Max 5.25 V
Supply Voltage-Min 4.75 V
Supply Voltage-Nom 5 V
Surface Mount NO
Technology CMOS
Terminal Form THROUGH-HOLE
Terminal Pitch 2.54 mm
Terminal Position DUAL
Width 7.62 mm
会社名称Lattice Semiconductor Corporation
設立1983
所在地7th Floor, 111 SW 5th Avenue, Portland OR 97204
URLhttp://www.latticesemi.com/

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