型番 | 74LVCH16827APA |
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メーカー | IDT |
Additional Feature | WITH DUAL OUTPUT ENABLE |
Control Type | ENABLE LOW |
DLA Qualification | Not Qualified |
Family | LVC/LCX/Z |
J-STD-609 Code | e0 |
JESD-30 Code | R-PDSO-G56 |
JESD-609 Code | e0 |
Length (mm) | 14 |
Logic IC Type | BUS DRIVER |
Moisture Sensitivity Level | 1 |
Number of Bits | 10 |
Number of Functions | 2 |
Number of Ports | 2 |
Number of Terminals | 56 |
Operating Temperature-Max (Cel) | 85 |
Operating Temperature-Min (Cel) | -40 |
Output Characteristics | 3-STATE |
Output Low Current-Max (mA) | 24 |
Output Polarity | TRUE |
Package Body Material | PLASTIC/EPOXY |
Package Code | TSSOP |
Package Equivalence Code | TSSOP56,.3,20 |
Package Shape | RECTANGULAR |
Package Style | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH Meter |
Peak Reflow Temperature (Cel) | 240 |
Power Supplies (V) | 3.3 |
Propagation Delay (ns) | 5 |
Propagation Delay-Max@Nom-Sup (ns) | 4.1 |
Seated Height-Max (mm) | 1.1 |
Sub Category | Bus Driver/Transceivers |
Supply Voltage-Max (V) | 3.6 |
Supply Voltage-Min (V) | 2.7 |
Supply Voltage-Nom (V) | 3.3 |
Surface Mount | YES |
Technology | CMOS |
Temperature Grade | INDUSTRIAL |
Terminal Finish | TIN LEAD |
Terminal Form | GULL WING |
Terminal Pitch (mm) | 0.5 |
Terminal Position | DUAL |
Time@Peak Reflow Temperature-Max (s) | 20 |
Width (mm) | 6.1 |
会社名称 | Integrated Device Technology, Inc. |
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設立 | 1980 |
所在地 | 6024 Silver Creek Valley Road, San Jose, CA 95138 USA |
URL | http://www.idt.com/ |
74LVCH16827APA - IDT の商品詳細ページです。