71321LA55J Idt

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71321LA55J の詳細情報

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型番71321LA55J
メーカーIDT
Access Time-Max 55 ns
Access Time-Max (ns) 55
Additional Feature INTERRUPT FLAG; AUTOMATIC POWER-DOWN; BATTERY BACKUP
DLA Qualification Not Qualified
I/O Type COMMON
J-STD-609 Code e0
JESD-30 Code S-PQCC-J52
JESD-609 Code e3
Length (mm) 19.1262
Memory Density 16384 bit
Memory Density (bits) 16384
Memory IC Type APPLICATION SPECIFIC SRAM
Memory Organization 2KX8
Memory Width 8
Moisture Sensitivity Level 1
Number of Functions 1
Number of Ports 2
Number of Terminals 52
Number of Words 2048 words
Number of Words (words) 2048
Number of Words Code 2K
Operating Mode ASYNCHRONOUS
Operating Temperature-Max (Cel) 70
Operating Temperature-Min (Cel) -40
Output Characteristics 3-STATE
Package Body Material PLASTIC/EPOXY
Package Code QCCJ
Package Equivalence Code LDCC52,.8SQ
Package Shape SQUARE
Package Style CHIP CARRIER Meter
Parallel/Serial PARALLEL
Peak Reflow Temperature (Cel) 225
Power Supplies (V) 5
Seated Height-Max (mm) 4.572
Standby Current-Max (A) 0.0015
Standby Voltage-Min (V) 2
Sub Category SRAMs
Supply Current-Max (mA) 110
Supply Voltage-Max (V) 5.5
Supply Voltage-Min (V) 4.5
Supply Voltage-Nom (V) 5
Surface Mount YES
Technology CMOS
Temperature Grade COMMERCIAL
Terminal Finish Matte Tin (Sn) - annealed
Terminal Form J BEND
Terminal Pitch (mm) 1.27
Terminal Position QUAD
Time@Peak Reflow Temperature-Max (s) 20
Width (mm) 19.1262
会社名称Integrated Device Technology, Inc.
設立1980
所在地6024 Silver Creek Valley Road, San Jose, CA 95138 USA
URLhttp://www.idt.com/

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