DM74LS503N データシート Fairchild

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アドバンストLS-TTL　トランジスタ・トランジスタ・ロジック|パッケージ： Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

DM74LS503N の詳細情報

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  • メーカー情報
型番DM74LS503N
メーカーFAIRCHILD
種別CMOS標準ロジックIC
データシートProduct_list_pdf
Additional Feature SUCCESSIVE APPROXIMATION REGISTER
Count Direction RIGHT
Family LS
JESD-30 Code R-PDIP-T16
JESD-609 Code e0
Length 19.304 mm
Load Capacitance (CL) 15 pF
Logic IC Type SERIAL IN PARALLEL OUT
Max Frequency@Nom-Sup 15000000 Hz
Number of Bits 8
Number of Functions 1
Number of Terminals 16
Operating Temperature-Max 70 Cel
Operating Temperature-Min 0 Cel
Output Polarity TRUE
Package Body Material PLASTIC/EPOXY
Package Code DIP
Package Equivalence Code DIP16,.3
Package Shape RECTANGULAR
Package Style IN-LINE Meter
Peak Reflow Temperature (Cel) NOT SPECIFIED
Power Supplies 5 V
Power Supply Current-Max (ICC) 65 mA
Propagation Delay (tpd) 25 ns
Qualification Status Not Qualified
Seated Height-Max 5.08 mm
Sub Category Shift Registers
Supply Voltage-Max (Vsup) 5.25 V
Supply Voltage-Min (Vsup) 4.75 V
Supply Voltage-Nom (Vsup) 5 V
Surface Mount NO
Technology TTL
Temperature Grade COMMERCIAL
Terminal Finish TIN LEAD
Terminal Form THROUGH-HOLE
Terminal Pitch 2.54 mm
Terminal Position DUAL
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
Trigger Type POSITIVE EDGE
Width 7.62 mm
fmax-Min 15 MHz
会社名称Fairchild Semiconductor Corporation
設立1957
所在地3030 Orchard Parkway San Jose, CA 95134 United States
URLhttp://www.fairchildsemi.com/

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