2回路JK-フリップフロップ(PRESET/CLR付き)|パッケージ: Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
型番 | DM7476N |
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メーカー | FAIRCHILD |
種別 | CMOS標準ロジックIC |
データシート | ![]() |
Additional Feature | MASTER SLAVE OPERATION |
Family | TTL/H/L |
JESD-30 Code | R-PDIP-T16 |
JESD-609 Code | e0 |
Length | 19.305 mm |
Load Capacitance (CL) | 15 pF |
Logic IC Type | J-K FLIP-FLOP |
Max Frequency@Nom-Sup | 15000000 Hz |
Max I(ol) | 0.016 Amp |
Number of Bits | 2 |
Number of Functions | 2 |
Number of Terminals | 16 |
Operating Temperature-Max | 70 Cel |
Operating Temperature-Min | 0 Cel |
Output Polarity | COMPLEMENTARY |
Package Body Material | PLASTIC/EPOXY |
Package Code | DIP |
Package Equivalence Code | DIP16,.3 |
Package Shape | RECTANGULAR |
Package Style | IN-LINE Meter |
Peak Reflow Temperature (Cel) | NOT SPECIFIED |
Power Supplies | 5 V |
Power Supply Current-Max (ICC) | 17 mA |
Propagation Delay (tpd) | 40 ns |
Qualification Status | Not Qualified |
Seated Height-Max | 5.08 mm |
Sub Category | FF/Latches |
Supply Voltage-Max (Vsup) | 5.25 V |
Supply Voltage-Min (Vsup) | 4.75 V |
Supply Voltage-Nom (Vsup) | 5 V |
Surface Mount | NO |
Technology | TTL |
Temperature Grade | COMMERCIAL |
Terminal Finish | TIN LEAD |
Terminal Form | THROUGH-HOLE |
Terminal Pitch | 2.54 mm |
Terminal Position | DUAL |
Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
Trigger Type | MASTER-SLAVE |
Width | 7.62 mm |
fmax-Min | 15 MHz |
会社名称 | Fairchild Semiconductor Corporation |
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設立 | 1957 |
所在地 | 3030 Orchard Parkway San Jose, CA 95134 United States |
URL | http://www.fairchildsemi.com/ |
DM7476N - FAIRCHILD の商品詳細ページです。