CMOS標準ロジックIC|Programmable タイマ | 14ピン|パッケージ: Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
| 型番 | CD4541BCNNL |
|---|---|
| メーカー | FAIRCHILD |
| 種別 | CMOS標準ロジックIC |
| データシート | ![]() |
| Count Direction | UP |
| Family | 4000/14000/40000 |
| JESD-30 Code | R-PDIP-T14 |
| JESD-609 Code | e3 |
| Length | 19.18 mm |
| Load/Preset Input | YES |
| Logic IC Type | BINARY COUNTER |
| Mode of Operation | ASYNCHRONOUS |
| Number of Bits | 14 |
| Number of Functions | 1 |
| Number of Terminals | 14 |
| Operating Temperature-Max | 125 Cel |
| Operating Temperature-Min | -55 Cel |
| Package Body Material | PLASTIC/EPOXY |
| Package Code | DIP |
| Package Shape | RECTANGULAR |
| Package Style | IN-LINE Meter |
| Propagation Delay (tpd) | 1300 ns |
| Qualification Status | Not Qualified |
| Seated Height-Max | 5.08 mm |
| Supply Voltage-Max (Vsup) | 15 V |
| Supply Voltage-Min (Vsup) | 3 V |
| Supply Voltage-Nom (Vsup) | 5 V |
| Surface Mount | NO |
| Technology | CMOS |
| Temperature Grade | MILITARY |
| Terminal Finish | MATTE TIN |
| Terminal Form | THROUGH-HOLE |
| Terminal Pitch | 2.54 mm |
| Terminal Position | DUAL |
| Trigger Type | NEGATIVE EDGE |
| Width | 7.62 mm |
| fmax-Min | 4 MHz |
| 会社名称 | Fairchild Semiconductor Corporation |
|---|---|
| 設立 | 1957 |
| 所在地 | 3030 Orchard Parkway San Jose, CA 95134 United States |
| URL | http://www.fairchildsemi.com/ |
CD4541BCNNL - FAIRCHILD の商品詳細ページです。