CD4515BCN データシート Fairchild

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CMOS標準ロジックIC|パッケージ： Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

CD4515BCN の詳細情報

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  • メーカー情報
型番CD4515BCN
メーカーFAIRCHILD
種別CMOS標準ロジックIC
データシートProduct_list_pdf
Additional Feature ADDRESS LATCHES
Family 4000/14000/40000
Input Conditioning LATCHED
JESD-30 Code R-PDIP-T24
JESD-609 Code e0
Length 31.915 mm
Load Capacitance (CL) 50 pF
Logic IC Type OTHER DECODER/DRIVER
Number of Functions 1
Number of Terminals 24
Operating Temperature-Max 85 Cel
Operating Temperature-Min -55 Cel
Output Polarity TRUE
Package Body Material PLASTIC/EPOXY
Package Code DIP
Package Equivalence Code DIP24,.6
Package Shape RECTANGULAR
Package Style IN-LINE Meter
Peak Reflow Temperature (Cel) NOT SPECIFIED
Power Supplies 3/15 V
Prop. Delay@Nom-Sup 1100 ns
Propagation Delay (tpd) 1100 ns
Qualification Status Not Qualified
Seated Height-Max 5.334 mm
Sub Category Decoder/Drivers
Supply Voltage-Max (Vsup) 15 V
Supply Voltage-Min (Vsup) 3 V
Supply Voltage-Nom (Vsup) 5 V
Surface Mount NO
Technology CMOS
Temperature Grade INDUSTRIAL
Terminal Finish Tin/Lead (Sn/Pb)
Terminal Form THROUGH-HOLE
Terminal Pitch 2.54 mm
Terminal Position DUAL
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
Width 15.24 mm
会社名称Fairchild Semiconductor Corporation
設立1957
所在地3030 Orchard Parkway San Jose, CA 95134 United States
URLhttp://www.fairchildsemi.com/

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