CD4046BCN データシート Fairchild

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CMOS標準ロジックIC|PLL(電圧制御発振器+位相比較器) | 16ピン|パッケージ： Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

CD4046BCN の詳細情報

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  • メーカー情報
型番CD4046BCN
メーカーFAIRCHILD
種別CMOS標準ロジックIC
データシートProduct_list_pdf
Additional Feature WITH TWO PHASE COMPARATORS
Analog IC - Other Type PHASE LOCKED LOOP
JESD-30 Code R-PDIP-T16
JESD-609 Code e0
Length 19.304 mm
Moisture Sensitivity Level 1
Number of Functions 1
Number of Terminals 16
Operating Temperature-Max 85 Cel
Operating Temperature-Min -55 Cel
Package Body Material PLASTIC/EPOXY
Package Code DIP
Package Equivalence Code DIP16,.3
Package Shape RECTANGULAR
Package Style IN-LINE Meter
Peak Reflow Temperature (Cel) 260
Power Supplies 5/15 V
Qualification Status Not Qualified
Seated Height-Max 5.08 mm
Sub Category PLL or Frequency Synthesis Circuits
Supply Current-Max (Isup) 1.8 mA
Supply Voltage-Max (Vsup) 15 V
Supply Voltage-Min (Vsup) 3 V
Supply Voltage-Nom (Vsup) 5 V
Surface Mount NO
Technology CMOS
Temperature Grade INDUSTRIAL
Terminal Finish TIN LEAD
Terminal Form THROUGH-HOLE
Terminal Pitch 2.54 mm
Terminal Position DUAL
Time@Peak Reflow Temperature-Max (s) 40
Width 7.62 mm
会社名称Fairchild Semiconductor Corporation
設立1957
所在地3030 Orchard Parkway San Jose, CA 95134 United States
URLhttp://www.fairchildsemi.com/

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