CD4021BCNNL データシート Fairchild

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CMOS標準ロジックIC|8ビット Shift レジスタ | 16ピン|パッケージ： Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

CD4021BCNNL の詳細情報

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  • メーカー情報
型番CD4021BCNNL
メーカーFAIRCHILD
種別CMOS標準ロジックIC
データシートProduct_list_pdf
Additional Feature OUTPUTS ALSO AVAILABLE AT 6TH AND 7TH STAGE OF THE SHIFT REGISTER
Count Direction RIGHT
Family 4000/14000/40000
JESD-30 Code R-PDIP-T16
JESD-609 Code e3
Length 19.305 mm
Logic IC Type PARALLEL IN SERIAL OUT
Max Frequency@Nom-Sup 2500000 Hz
Number of Bits 8
Number of Functions 1
Number of Terminals 16
Operating Temperature-Max 125 Cel
Operating Temperature-Min -55 Cel
Output Polarity TRUE
Package Body Material PLASTIC/EPOXY
Package Code DIP
Package Equivalence Code DIP16,.3
Package Shape RECTANGULAR
Package Style IN-LINE Meter
Power Supplies 5/15 V
Propagation Delay (tpd) 350 ns
Qualification Status Not Qualified
Seated Height-Max 5.08 mm
Sub Category Shift Registers
Supply Voltage-Max (Vsup) 15 V
Supply Voltage-Min (Vsup) 3 V
Supply Voltage-Nom (Vsup) 5 V
Surface Mount NO
Technology CMOS
Temperature Grade MILITARY
Terminal Finish MATTE TIN
Terminal Form THROUGH-HOLE
Terminal Pitch 2.54 mm
Terminal Position DUAL
Trigger Type POSITIVE EDGE
Width 7.62 mm
fmax-Min 8 MHz
会社名称Fairchild Semiconductor Corporation
設立1957
所在地3030 Orchard Parkway San Jose, CA 95134 United States
URLhttp://www.fairchildsemi.com/

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