74VHC112SJ データシート Fairchild

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CMOS標準ロジックIC|パッケージ： Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC112SJ の詳細情報

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型番74VHC112SJ
メーカーFAIRCHILD
種別CMOS標準ロジックIC
データシートProduct_list_pdf
Family AHC/VHC
JESD-30 Code R-PDSO-G16
JESD-609 Code e3
Length 10.1 mm
Load Capacitance (CL) 50 pF
Logic IC Type J-K FLIP-FLOP
Max Frequency@Nom-Sup 110000000 Hz
Max I(ol) 0.008 Amp
Moisture Sensitivity Level 1
Number of Bits 2
Number of Functions 2
Number of Terminals 16
Operating Temperature-Max 85 Cel
Operating Temperature-Min -40 Cel
Output Polarity COMPLEMENTARY
Package Body Material PLASTIC/EPOXY
Package Code SOP
Package Equivalence Code SOP16,.3
Package Shape RECTANGULAR
Package Style SMALL OUTLINE Meter
Packing Method RAIL
Peak Reflow Temperature (Cel) 260
Power Supplies 2/5.5 V
Prop. Delay@Nom-Sup 12 ns
Propagation Delay (tpd) 12 ns
Qualification Status Not Qualified
Seated Height-Max 2.1 mm
Sub Category FF/Latches
Supply Voltage-Max (Vsup) 5.5 V
Supply Voltage-Min (Vsup) 2 V
Supply Voltage-Nom (Vsup) 3.3 V
Surface Mount YES
Technology CMOS
Temperature Grade INDUSTRIAL
Terminal Finish MATTE TIN
Terminal Form GULL WING
Terminal Pitch 1.27 mm
Terminal Position DUAL
Trigger Type NEGATIVE EDGE
Width 5.3 mm
fmax-Min 110 MHz
会社名称Fairchild Semiconductor Corporation
設立1957
所在地3030 Orchard Parkway San Jose, CA 95134 United States
URLhttp://www.fairchildsemi.com/

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