74LVX74MTC データシート Fairchild

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CMOS標準ロジックIC|パッケージ： Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide | Lead free

74LVX74MTC の詳細情報

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型番74LVX74MTC
メーカーFAIRCHILD
種別CMOS標準ロジックIC
データシートProduct_list_pdf
Family LV/LV-A/LVX/H
JESD-30 Code R-PDSO-G14
JESD-609 Code e0
Length 5 mm
Load Capacitance (CL) 50 pF
Logic IC Type D FLIP-FLOP
Max Frequency@Nom-Sup 50000000 Hz
Max I(ol) 0.004 Amp
Moisture Sensitivity Level 1
Number of Bits 1
Number of Functions 2
Number of Terminals 14
Operating Temperature-Max 85 Cel
Operating Temperature-Min -40 Cel
Output Polarity COMPLEMENTARY
Package Body Material PLASTIC/EPOXY
Package Code TSSOP
Package Equivalence Code TSSOP14,.25
Package Shape RECTANGULAR
Package Style SMALL OUTLINE, THIN PROFILE, SHRINK PITCH Meter
Packing Method TR
Peak Reflow Temperature (Cel) 260
Power Supplies 3.3 V
Prop. Delay@Nom-Sup 15 ns
Propagation Delay (tpd) 22 ns
Qualification Status Not Qualified
Seated Height-Max 1.1 mm
Sub Category FF/Latches
Supply Voltage-Max (Vsup) 3.6 V
Supply Voltage-Min (Vsup) 2 V
Supply Voltage-Nom (Vsup) 2.7 V
Surface Mount YES
Technology CMOS
Temperature Grade INDUSTRIAL
Terminal Finish MATTE TIN
Terminal Form GULL WING
Terminal Pitch 0.65 mm
Terminal Position DUAL
Time@Peak Reflow Temperature-Max (s) 30
Trigger Type POSITIVE EDGE
Width 4.4 mm
fmax-Min 80 MHz
会社名称Fairchild Semiconductor Corporation
設立1957
所在地3030 Orchard Parkway San Jose, CA 95134 United States
URLhttp://www.fairchildsemi.com/

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