74LVX138MTC データシート Fairchild

74LVX138MTC - FAIRCHILD の商品詳細ページです。

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CMOS標準ロジックIC|パッケージ: Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide | Lead free

74LVX138MTC の詳細情報

  • 仕様・詳細
  • メーカー情報
型番74LVX138MTC
メーカーFAIRCHILD
種別CMOS標準ロジックIC
データシートProduct_list_pdf
Additional Feature THREE ENABLE INPUTS
Family LV/LV-A/LVX/H
Input Conditioning STANDARD
JESD-30 Code R-PDSO-G16
JESD-609 Code e0
Length 5 mm
Load Capacitance (CL) 50 pF
Logic IC Type OTHER DECODER/DRIVER
Max I(ol) 0.004 Amp
Moisture Sensitivity Level 1
Number of Functions 1
Number of Terminals 16
Operating Temperature-Max 85 Cel
Operating Temperature-Min -40 Cel
Output Characteristics 3-STATE
Output Polarity INVERTED
Package Body Material PLASTIC/EPOXY
Package Code TSSOP
Package Equivalence Code TSSOP16,.25
Package Shape RECTANGULAR
Package Style SMALL OUTLINE, THIN PROFILE, SHRINK PITCH Meter
Packing Method TR
Peak Reflow Temperature (Cel) 260
Power Supplies 3.3 V
Prop. Delay@Nom-Sup 14 ns
Propagation Delay (tpd) 14 ns
Qualification Status Not Qualified
Seated Height-Max 1.1 mm
Sub Category Decoder/Drivers
Supply Voltage-Max (Vsup) 3.6 V
Supply Voltage-Min (Vsup) 2 V
Supply Voltage-Nom (Vsup) 2.7 V
Surface Mount YES
Technology CMOS
Temperature Grade INDUSTRIAL
Terminal Finish NICKEL PALLADIUM GOLD
Terminal Form GULL WING
Terminal Pitch 0.65 mm
Terminal Position DUAL
Time@Peak Reflow Temperature-Max (s) 30
Width 4.4 mm
会社名称Fairchild Semiconductor Corporation
設立1957
所在地3030 Orchard Parkway San Jose, CA 95134 United States
URLhttp://www.fairchildsemi.com/

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