74AC520PC データシート Fairchild

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74AC520PC
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2営業日以内に回答いたします

Advanced CMOSロジックIC|パッケージ: Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide | Lead free

74AC520PC の詳細情報

  • 仕様・詳細
  • メーカー情報
型番74AC520PC
メーカーFAIRCHILD
種別Advanced CMOSロジックIC
データシートProduct_list_pdf
Additional Feature ALSO WORKS WITH 5V VCC
Family AC
JESD-30 Code R-PDIP-T20
JESD-609 Code e0
Length 24.892 mm
Load Capacitance (CL) 50 pF
Logic IC Type IDENTITY COMPARATOR
Number of Bits 8
Number of Functions 1
Number of Terminals 20
Operating Temperature-Max 85 Cel
Operating Temperature-Min -40 Cel
Output Polarity INVERTED
Package Body Material PLASTIC/EPOXY
Package Code DIP
Package Equivalence Code DIP20,.3
Package Shape RECTANGULAR
Package Style IN-LINE Meter
Peak Reflow Temperature (Cel) NOT SPECIFIED
Power Supplies 3.3/5 V
Propagation Delay (tpd) 13.5 ns
Qualification Status Not Qualified
Seated Height-Max 5.08 mm
Sub Category Arithmetic Circuits
Supply Voltage-Max (Vsup) 3.6 V
Supply Voltage-Min (Vsup) 2 V
Supply Voltage-Nom (Vsup) 3 V
Surface Mount NO
Technology CMOS
Temperature Grade INDUSTRIAL
Terminal Finish TIN LEAD
Terminal Form THROUGH-HOLE
Terminal Pitch 2.54 mm
Terminal Position DUAL
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
Width 7.62 mm
会社名称Fairchild Semiconductor Corporation
設立1957
所在地3030 Orchard Parkway San Jose, CA 95134 United States
URLhttp://www.fairchildsemi.com/

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