CY7C382A1JC Cypress

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CY7C382A1JC の詳細情報

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型番CY7C382A1JC
メーカーCYPRESS
Additional Feature MAX. 56 I/OS; OTP BASED
Clock Frequency-Max 242.5 MHz
Combinatorial Delay of a CLB-Max 6.384 ns
JESD-30 Code S-PQCC-J68
JESD-609 Code e0
Length 24.2316 mm
Number of CLBs 96
Number of Equivalent Gates 1000
Number of Inputs 64
Number of Logic Cells 96
Number of Outputs 56
Number of Terminals 68
Operating Temperature-Max 70 Cel
Operating Temperature-Min 0 Cel
Organization 96 CLBS, 1000 GATES
Package Body Material PLASTIC/EPOXY
Package Code QCCJ
Package Equivalence Code LDCC68,1.0SQ
Package Shape SQUARE
Package Style CHIP CARRIER Meter
Power Supplies 5 V
Programmable Logic Type FIELD PROGRAMMABLE GATE ARRAY
Qualification Status Not Qualified
Seated Height-Max 5.08 mm
Sub Category Field Programmable Gate Arrays
Supply Voltage-Max 5.25 V
Supply Voltage-Min 4.75 V
Supply Voltage-Nom 5 V
Surface Mount YES
Technology CMOS
Temperature Grade COMMERCIAL
Terminal Finish TIN LEAD
Terminal Form J BEND
Terminal Pitch 1.27 mm
Terminal Position QUAD
Width 24.2316 mm
会社名称Cypress Semiconductor Corporation.
所在地198 Champion Court San Jose, CA 95134 USA
URLhttp://www.cypress.com/

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