| 型番 | PEEL173P-30 |
|---|
| メーカー | AMI |
|---|
| データシート |  |
| Additional Feature |
PROGRAMMABLE OUTPUT POLARITY |
| Architecture |
PLA-TYPE |
| Clock Frequency-Max |
16.7 MHz |
| JESD-30 Code |
R-PDIP-T24 |
| JESD-609 Code |
e0 |
| Number of Dedicated Inputs |
12 |
| Number of I/O Lines |
10 |
| Number of Inputs |
22 |
| Number of Outputs |
10 |
| Number of Product Terms |
42 |
| Number of Terminals |
24 |
| Operating Temperature-Max |
70 Cel |
| Operating Temperature-Min |
0 Cel |
| Organization |
12 DEDICATED INPUTS, 10 I/O |
| Output Function |
COMBINATORIAL |
| Package Body Material |
PLASTIC/EPOXY |
| Package Code |
DIP |
| Package Equivalence Code |
DIP24,.3 |
| Package Shape |
RECTANGULAR |
| Package Style |
IN-LINE Meter |
| Power Supplies |
5 V |
| Programmable Logic Type |
EE PLD |
| Propagation Delay |
30 ns |
| Qualification Status |
Not Qualified |
| Sub Category |
Programmable Logic Devices |
| Supply Voltage-Max |
5.25 V |
| Supply Voltage-Min |
4.75 V |
| Supply Voltage-Nom |
5 V |
| Surface Mount |
NO |
| Technology |
CMOS |
| Temperature Grade |
COMMERCIAL |
| Terminal Finish |
Tin/Lead (Sn/Pb) |
| Terminal Form |
THROUGH-HOLE |
| Terminal Pitch |
2.54 mm |
| Terminal Position |
DUAL |
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