| 型番 | EPM5130JC-2 |
|---|
| メーカー | ALTERA |
|---|
| データシート |  |
| Additional Feature |
LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK |
| Clock Frequency-Max |
40 MHz |
| In-System Programmable |
NO |
| JESD-30 Code |
S-CQCC-J84 |
| JESD-609 Code |
e0 |
| JTAG BST |
NO |
| Length |
29.21 mm |
| Number of Dedicated Inputs |
19 |
| Number of I/O Lines |
48 |
| Number of Macro Cells |
128 |
| Number of Terminals |
84 |
| Operating Temperature-Max |
70 Cel |
| Operating Temperature-Min |
0 Cel |
| Organization |
19 DEDICATED INPUTS, 48 I/O |
| Output Function |
MACROCELL |
| Package Body Material |
CERAMIC, METAL-SEALED COFIRED |
| Package Code |
WQCCJ |
| Package Equivalence Code |
LDCC84,1.2SQ |
| Package Shape |
SQUARE |
| Package Style |
CHIP CARRIER, WINDOW Meter |
| Peak Reflow Temperature (Cel) |
220 |
| Power Supplies |
5 V |
| Programmable Logic Type |
UV PLD |
| Propagation Delay |
45 ns |
| Qualification Status |
Not Qualified |
| Seated Height-Max |
5.08 mm |
| Sub Category |
Programmable Logic Devices |
| Supply Voltage-Max |
5.25 V |
| Supply Voltage-Min |
4.75 V |
| Supply Voltage-Nom |
5 V |
| Surface Mount |
YES |
| Technology |
CMOS |
| Temperature Grade |
COMMERCIAL |
| Terminal Finish |
TIN LEAD |
| Terminal Form |
J BEND |
| Terminal Pitch |
1.27 mm |
| Terminal Position |
QUAD |
| Width |
29.21 mm |
EPM5130JC-2 - ALTERA の商品詳細ページです。