| 型番 | EPM5130GM |
|---|
| メーカー | ALTERA |
|---|
| データシート |  |
| Additional Feature |
128 MACROCELLS; SHARED INPUT/CLOCK; SHARED PRODUCT TERMS |
| Clock Frequency-Max |
33.3 MHz |
| In-System Programmable |
NO |
| JESD-30 Code |
S-CPGA-P100 |
| JESD-609 Code |
e0 |
| JTAG BST |
NO |
| Length |
33.528 mm |
| Number of Dedicated Inputs |
19 |
| Number of I/O Lines |
64 |
| Number of Macro Cells |
128 |
| Number of Terminals |
100 |
| Operating Temperature-Max |
125 Cel |
| Operating Temperature-Min |
-55 Cel |
| Organization |
19 DEDICATED INPUTS, 64 I/O |
| Output Function |
MACROCELL |
| Package Body Material |
CERAMIC, METAL-SEALED COFIRED |
| Package Code |
WPGA |
| Package Equivalence Code |
PGA100M,13X13 |
| Package Shape |
SQUARE |
| Package Style |
GRID ARRAY, WINDOW Meter |
| Peak Reflow Temperature (Cel) |
220 |
| Power Supplies |
5 V |
| Programmable Logic Type |
UV PLD |
| Propagation Delay |
45 ns |
| Qualification Status |
Not Qualified |
| Screening Level |
38535Q/M;38534H;883B |
| Seated Height-Max |
3.81 mm |
| Sub Category |
Programmable Logic Devices |
| Supply Voltage-Max |
5.5 V |
| Supply Voltage-Min |
4.5 V |
| Supply Voltage-Nom |
5 V |
| Surface Mount |
NO |
| Technology |
CMOS |
| Temperature Grade |
MILITARY |
| Terminal Finish |
TIN LEAD |
| Terminal Form |
PIN/PEG |
| Terminal Pitch |
2.54 mm |
| Terminal Position |
PERPENDICULAR |
| Width |
33.528 mm |
EPM5130GM - ALTERA の商品詳細ページです。