EPM5032DC-25 データシート Altera

EPM5032DC-25 - ALTERA の商品詳細ページです。

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EPM5032DC-25 の詳細情報

  • 仕様・詳細
  • メーカー情報
型番EPM5032DC-25
メーカーALTERA
データシートProduct_list_pdf
Additional Feature MACROCELLS INTERCONNECTED BY PIA; 1 LAB; 32 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
Architecture PAL-TYPE
Clock Frequency-Max 62.5 MHz
JESD-30 Code R-GDIP-T28
JESD-609 Code e0
Length 36.83 mm
Number of Dedicated Inputs 7
Number of I/O Lines 16
Number of Inputs 24
Number of Outputs 16
Number of Product Terms 320
Number of Terminals 28
Operating Temperature-Max 70 Cel
Operating Temperature-Min 0 Cel
Organization 7 DEDICATED INPUTS, 16 I/O
Output Function MACROCELL
Package Body Material CERAMIC, GLASS-SEALED
Package Code WDIP
Package Equivalence Code DIP28,.3
Package Shape RECTANGULAR
Package Style IN-LINE, WINDOW Meter
Peak Reflow Temperature (Cel) 220
Power Supplies 5 V
Programmable Logic Type UV PLD
Propagation Delay 25 ns
Qualification Status Not Qualified
Seated Height-Max 5.08 mm
Sub Category Programmable Logic Devices
Supply Voltage-Max 5.25 V
Supply Voltage-Min 4.75 V
Supply Voltage-Nom 5 V
Surface Mount NO
Technology CMOS
Temperature Grade COMMERCIAL
Terminal Finish TIN LEAD
Terminal Form THROUGH-HOLE
Terminal Pitch 2.54 mm
Terminal Position DUAL
Width 7.62 mm
会社名称アルテラ
設立1983
所在地101 Innovation Drive San Jose, CA 95134 United States
URLhttp://www.altera.com/

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