EP610DC15 データシート Altera

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EP610DC15 の詳細情報

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型番EP610DC15
メーカーALTERA
データシートProduct_list_pdf
Architecture PAL-TYPE
Clock Frequency-Max 71.4 MHz
JESD-30 Code R-GDIP-T24
JESD-609 Code e0
Number of Dedicated Inputs 4
Number of I/O Lines 16
Number of Inputs 20
Number of Outputs 16
Number of Product Terms 160
Number of Terminals 24
Operating Temperature-Max 70 Cel
Operating Temperature-Min 0 Cel
Organization 4 DEDICATED INPUTS, 16 I/O
Output Function MACROCELL
Package Body Material CERAMIC, GLASS-SEALED
Package Code DIP
Package Equivalence Code DIP24,.3
Package Shape RECTANGULAR
Package Style IN-LINE Meter
Peak Reflow Temperature (Cel) 220
Power Supplies 5 V
Programmable Logic Type UV PLD
Propagation Delay 17 ns
Qualification Status Not Qualified
Sub Category Programmable Logic Devices
Supply Voltage-Max 5.25 V
Supply Voltage-Min 4.75 V
Supply Voltage-Nom 5 V
Surface Mount NO
Technology CMOS
Temperature Grade COMMERCIAL
Terminal Finish TIN LEAD
Terminal Form THROUGH-HOLE
Terminal Pitch 2.54 mm
Terminal Position DUAL
会社名称アルテラ
設立1983
所在地101 Innovation Drive San Jose, CA 95134 United States
URLhttp://www.altera.com/

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