EP20K400FI6722V データシート Altera

EP20K400FI6722V - ALTERA の商品詳細ページです。

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EP20K400FI6722V の詳細情報

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  • メーカー情報
型番EP20K400FI6722V
メーカーALTERA
データシートProduct_list_pdf
JESD-30 Code S-PBGA-B672
JESD-609 Code e0
Length 27 mm
Moisture Sensitivity Level 3
Number of I/O Lines 502
Number of Inputs 496
Number of Logic Cells 16640
Number of Outputs 496
Number of Terminals 672
Organization 502 I/O
Output Function MACROCELL
Package Body Material PLASTIC/EPOXY
Package Code BGA
Package Equivalence Code BGA672,26X26,40
Package Shape SQUARE
Package Style GRID ARRAY Meter
Peak Reflow Temperature (Cel) 220
Power Supplies 2.5,2.5/3.3 V
Programmable Logic Type LOADABLE PLD
Propagation Delay 3.1 ns
Qualification Status Not Qualified
Seated Height-Max 2.1 mm
Sub Category Field Programmable Gate Arrays
Supply Voltage-Max 2.625 V
Supply Voltage-Min 2.375 V
Supply Voltage-Nom 2.5 V
Surface Mount YES
Technology CMOS
Terminal Finish TIN LEAD
Terminal Form BALL
Terminal Pitch 1 mm
Terminal Position BOTTOM
Time@Peak Reflow Temperature-Max (s) 20
Width 27 mm
会社名称アルテラ
設立1983
所在地101 Innovation Drive San Jose, CA 95134 United States
URLhttp://www.altera.com/

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