EP20K400BC6521XV データシート Altera

EP20K400BC6521XV - ALTERA の商品詳細ページです。

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EP20K400BC6521XV の詳細情報

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  • メーカー情報
型番EP20K400BC6521XV
メーカーALTERA
データシートProduct_list_pdf
JESD-30 Code S-PBGA-B652
JESD-609 Code e0
Length 45 mm
Moisture Sensitivity Level 3
Number of I/O Lines 502
Number of Inputs 496
Number of Logic Cells 16640
Number of Outputs 496
Number of Terminals 652
Operating Temperature-Max 85 Cel
Operating Temperature-Min 0 Cel
Organization 502 I/O
Output Function MACROCELL
Package Body Material PLASTIC/EPOXY
Package Code LBGA
Package Equivalence Code BGA652,35X35,50
Package Shape SQUARE
Package Style GRID ARRAY, LOW PROFILE Meter
Peak Reflow Temperature (Cel) 220
Power Supplies 2.5,2.5/3.3 V
Programmable Logic Type LOADABLE PLD
Propagation Delay 2.5 ns
Qualification Status Not Qualified
Seated Height-Max 1.63 mm
Sub Category Field Programmable Gate Arrays
Supply Voltage-Max 2.625 V
Supply Voltage-Min 2.375 V
Supply Voltage-Nom 2.5 V
Surface Mount YES
Technology CMOS
Temperature Grade OTHER
Terminal Finish TIN LEAD
Terminal Form BALL
Terminal Pitch 1.27 mm
Terminal Position BOTTOM
Time@Peak Reflow Temperature-Max (s) 20
Width 45 mm
会社名称アルテラ
設立1983
所在地101 Innovation Drive San Jose, CA 95134 United States
URLhttp://www.altera.com/

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