EP20K200RC208-2 データシート Altera

EP20K200RC208-2 - ALTERA の商品詳細ページです。

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EP20K200RC208-2 の詳細情報

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型番EP20K200RC208-2
メーカーALTERA
データシートProduct_list_pdf
Clock Frequency-Max 34 MHz
JESD-30 Code S-PQFP-G208
JESD-609 Code e0
Length 28 mm
Number of Dedicated Inputs 4
Number of I/O Lines 144
Number of Inputs 138
Number of Logic Cells 8320
Number of Outputs 138
Number of Terminals 208
Operating Temperature-Max 85 Cel
Operating Temperature-Min 0 Cel
Organization 4 DEDICATED INPUTS, 144 I/O
Output Function MACROCELL
Package Body Material PLASTIC/EPOXY
Package Code FQFP
Package Equivalence Code HQFP208,1.2SQ,20
Package Shape SQUARE
Package Style FLATPACK, FINE PITCH Meter
Peak Reflow Temperature (Cel) 220
Power Supplies 2.5,2.5/3.3 V
Programmable Logic Type LOADABLE PLD
Propagation Delay 0.4 ns
Qualification Status Not Qualified
Seated Height-Max 4.1 mm
Sub Category Field Programmable Gate Arrays
Supply Voltage-Max 2.625 V
Supply Voltage-Min 2.375 V
Supply Voltage-Nom 2.5 V
Surface Mount YES
Technology CMOS
Temperature Grade OTHER
Terminal Finish MATTE TIN
Terminal Form GULL WING
Terminal Pitch 0.5 mm
Terminal Position QUAD
Width 28 mm
会社名称アルテラ
設立1983
所在地101 Innovation Drive San Jose, CA 95134 United States
URLhttp://www.altera.com/

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